The invention relates to the field of automatic test generation, particularly towards delay line testing.
Delay lines are used in many applications, ranging from delay-locked loops to pulse-width modulators. Delay lines generally consist of a set of smaller delay elements stacked one after another to form a longer delay line. The delay line can be tapped at various points, referred to henceforth as a xe2x80x9ctapxe2x80x9dpreferably with equal distribution, as shown in FIG. 1A. An important attribute of a delay line is its linearity. Linearity is a measure of how closely the xe2x80x9cdelay vs. tapsxe2x80x9d curve approximates a straight line. A chain of N taps has a delay of N*"psgr", where "psgr" is the delay associated with each tap. Ideally, the chain is perfectly linear. In reality, the non-linearity must be evaluated. For standard compliance testing, a quantifiable measurement technique and acceptance criteria must be developed.
Two types of non-linearities, differential non-linearity (DNL) and integral non-linearity (INL), can occur in a delay chain. DNL is a comparison of the delay difference of two taps to the theoretical value. If one tap measures a while the next measures xcex2, the DNL would be |"psgr"-(xcex2-xcex1)|, where "psgr" is the theoretical value of a single tap. The calculated DNL can then be compared to an acceptable tolerance. This process is then repeated while traversing the delay chain to ensure each tap is within tolerance. The INL measures how closely the delay vs. taps curve approximates a straight line, as shown in FIG. 1B. INL is a result of imperfect DNL. Some delay values may be smaller than the ideal, while other taps have larger than ideal delay values. This leads to the xe2x80x9cbowingxe2x80x9d of the line, shown in FIG. 1B. INL is a measure of how far off each point is from the theoretical line that connects the two endpoints. Again, this INL number can then be compared to a desired tolerance.
Currently, delay lines are evaluated using a tester to measure delay values or each tap of the delay chain. Afterwards, calculations are performed to determine the DNL and the ideal line for the INL. The measured values are then compared against the theoretical limits to determine if the part is within specification. This measurement technique requires programming the delay chain to the appropriate value and then stimulating the input with a clock edge. The tester then strobes the output. Since the tester needs to find the exact location of the clock edge, the tester needs to strobe for both a low and a high value (for rising clock edge). The test is a repetitive process as each test run requires changing the strobes to locate the transition edge. A standard binary search algorithm determines the number of iterations while the upper and lower bounds are determined by the clock period.
The prior art method is slow due to three main factors. First, the tester is used in a non-optimum manner. Digital testers are optimized for comparing ones and zeroes against an expected value not for making precision measurements. Second, the tester is slow in performing the computations since it does not perform them in real-time. Third, the method does not produce real-time failures, which are important in a production test environment. A real-time test failure flags at the time the failure occurs. This prior art method does not stop until the measurements, calculations, and comparisons against the specified limits are completed.
Additionally, smaller delay values are being measured. Delay values are rapidly approaching the minimum resolution of the tester itself. Such small values make most tests unfeasible except for gross monotonicity. Monotonicity testing alone is insufficient qualification as it only confirms that the derivative of the delay curve corresponds to the direction that the chain is being measured. There is insufficient data to fully characterize a delay chain.
The present invention provides both differential and integral non-linearity measurement capabilities with a minimum of additional hardware and a test time reduction of several orders of magnitude. The test circuit for N delay lines includes a ring oscillator that has a select signal and an output. A counter is connected in parallel with the ring oscillator. An arithmetic logic unit receives a xe2x80x9cCOMPARExe2x80x9d value from a register and the counter output. An upper and a lower bound register store acceptable tolerances for non-linearity. Each comparator, upper and lower bound, receives the tolerance stored in the corresponding register and the output of the arithmetic logic unit. An AND gate receives the outputs of the upper and lower bound comparators and generates a signal indicative of the state of the oscillator.
There are three measurement techniques that may be applied to the test circuit. In the first measurement technique, the incremental paths in the delay chain are compared to test linearity of the entire delay chain independent of process, voltage, and temperature. In the second measurement technique, the delay paths are adjusted to a known value. In the third measurement technique, the ratio of two paths is compared with a known ratio of delay.